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is61c64al issi ? copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. integrated silicon solution, inc. ? 1-800-379-4774 1 rev. a 03/16/06 features ? high-speed access time: 10 ns ? cmos low power operation ? 1 mw (typical) cmos standby ? 125 mw (typical) operating ? ttl compatible interface levels ? single 5v power supply ? fully static operation: no clock or refresh required ? lead-free available 8k x 8 high-speed cmos static ram description the issi is61c64al is a very high-speed, low power, 8192-word by 8-bit static ram. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 150 w (typical) with cmos input levels. easy memory expansion is provided by using one chip enable input, ce . the active low write enable ( we ) controls both writing and reading of the memory. the is61c64al is packaged in the jedec standard 28- pin, 300-mil soj, and tsop. functional block diagram a0-a12 ce oe we 8k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 march 2006
is61c64al issi ? 2 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/16/06 pin configuration 28-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 1 9 18 17 16 15 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vdd we nc a8 a 9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 pin descriptions a0-a12 address inputs ce chip enable 1 input oe output enable input we write enable input i/o0-i/o7 input/output nc no connect v dd power gnd ground truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc read h l l d out i cc write l l x d in i cc 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 1 9 18 17 16 15 14 13 12 11 10 9 8 oe a11 a 9 a8 nc we vdd nc a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 pin configuration 28-pin tsop (type 1)
1 2 3 4 5 6 7 8 9 10 11 12 is61c64al issi ? integrated silicon solution, inc. ? 1-800-379-4774 3 rev. a 03/16/06 absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.5 w i out dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range range ambient temperature speed v dd (1) commercial 0c to +70c -10 5v 5% industrial ?40c to +85c -10 5v 5% note: 1. if operated at 12ns, v dd range is 5v + 10%. dc electrical characteristics (over operating range) symbol parameter test conditions mi n. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v dd + 0.5 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd com. ?1 1 a ind. ?2 2 i lo output leakage gnd v out v dd , com. ?1 1 a outputs disabled ind. ?2 2 note: 1. v il = ?3.0v for pulse width less than 10 ns.
is61c64al issi ? 4 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/16/06 power supply characteristics (1) (over operating range) -10 -12 symbol parameter test conditions min. max. min. max. unit i cc 1 v dd operating v dd = max., ce = v il com. ? 20 ? 20 ma supply current i out = 0 ma, f = 0 ind. ? 25 ? 25 i cc 2 v dd dynamic operating v dd = max., ce = v il com. ? 45 ? 35 ma supply current i out = 0 ma, f = f max ind. ? 50 ? 45 typ. (2) 25 25 i sb 1 ttl standby current v dd = max., com. ? 1 ? 1 ma (ttl inputs) v in = v ih or v il ind. ? 2 ? 2 ce v ih , f = 0 i sb 2 cmos standby v dd = max., com. ? 350 ? 350 a current (cmos inputs) ce v dd ? 0.2v, ind. ? 450 ? 450 v in v dd ? 0.2v, or typ. (2) 200 200 v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 5v, t a = 25 o c. not 100% tested. capacitance (1,2) symbol parameter conditi ons max. unit c in input capacitance v in = 0v 8 pf c out output capacitance v out = 0v 10 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 5.0v.
1 2 3 4 5 6 7 8 9 10 11 12 is61c64al issi ? integrated silicon solution, inc. ? 1-800-379-4774 5 rev. a 03/16/06 ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1 and 2 ac test loads figure 2 480 5 pf including jig and scope 255 output 5v 480 30 pf including jig and scope 255 output 5v figure 1 read cycle switching characteristics (1) (over operating range) -10 ns -12 ns symbol parameter min. max min. max. unit t rc read cycle time 10 ? 12 ? ns t aa address access time ? 10 ? 12 ns t oha output hold time 2 ? 2 ? ns t acs ce access time ? 10 ? 12 ns t doe oe access time ? 6 ? 6 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzoe (2) oe to high-z output ? 5 ? 6 ns t lzcs (2) ce to low-z output 2 ? 3 ? ns t hzcs (2) ce to high-z output ? 5 ? 7 ns t pu (3) ce to power-up 0 ? 0 ? ns t pd (3) ce to power-down ? 10 ? 12 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
is61c64al issi ? 6 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/16/06 data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t acs t lzcs t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzcs notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2)
1 2 3 4 5 6 7 8 9 10 11 12 is61c64al issi ? integrated silicon solution, inc. ? 1-800-379-4774 7 rev. a 03/16/06 ac waveforms write cycle no. 1 ( we we we we we controlled) (1,2) data undefined t wc valid address t scs t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps write cycle switching characteristics (1,3) (over operating range) -10 ns -12 ns symbol parameter min. max min. max. unit t wc write cycle time 10 ? 12 ? ns t scs ce to write end 9 ? 10 ? ns t aw address setup time 9 ? 10 ? ns to write end t ha address hold 0 ? 0 ? ns from write end t sa address setup time 0 ? 0 ? ns t pwe 1 we pulse width ( oe low) 9 ? 9 ? ns t pwe 2 we pulse width ( oe high) 8 ? 8 ? ns t sd data setup to write end 7 ? 7 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 6 ? 6 ns t lzwe (2) we high to low-z output 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write.
is61c64al issi ? 8 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/16/06 write cycle no. 2 ( oe is high during write cycle) (1,2) write cycle no. 3 ( oe is low during write cycle) (1) notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
1 2 3 4 5 6 7 8 9 10 11 12 is61c64al issi ? integrated silicon solution, inc. ? 1-800-379-4774 9 rev. a 03/16/06 data retention switching characteristics symbol parameter test condition min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 5.5 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v com. ? 50 90 a v in v dd ? 0.2v, or v in v ss + 0.2v ind. ? 100 t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns note: 1. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested. data retention waveform ( ce ce ce ce ce controlled) vdd ce vdd - 0.2v t sdr t rdr v dr ce gnd 4.5v 2.2v data retention mode
is61c64al issi ? 10 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/16/06 ordering information industrial range: -40c to +85c speed (ns) order part no. package 10 IS61C64AL-10JI 300-mil plastic soj is61c64al-10jli 300-mil plastic soj, lead-free is61c64al-10ti plastic tsop is61c64al-10tli plastic tsop, lead-free
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 300-mil plastic soj package code: j notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches sym. min. typ. max. min. typ. max. n0. leads 24/26 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 17.02 17.27 0.670 0.680 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc seating plane 1 n e1 d e2 e b e a1 a b c a2
packaging information issi ? 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 millimeters inches sym. min. typ. max. min. typ. max. n0. leads 28 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 18.29 18.54 0.720 0.730 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc millimeters inches sym. min. typ. max. min. typ. max. n0. leads 32 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 20.83 21.08 0.820 0.830 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc 300-mil plastic soj package code: j
integrated silicon solution, inc. issi packaging information d seating plane b e c 1 e a1 a s h l a n plastic tsop - 28-pins package code: t (type i) plastic tsop (ttype i) millimeters inches symbol min max min max ref. std. no. leads 28 a 1.00 1.20 0.037 0.047 a1 0.05 0.20 0.002 0.008 b 0.16 0.27 0.006 0.011 c 0.10 0.20 0.004 0.008 d 7.90 8.10 0.308 0.316 e 11.70 11.90 0.456 0.465 h 13.20 13.60 0.515 0.531 e 0.55 bsc 0.022 bsc l 0.30 0.70 0.011 0.027 a 0 5 0 5 notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. pk13197t28 rev. b 01/31/97

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